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| 1 characteristics subject to change without notice 2051 4.4 3/15/01 SMH4803A preliminary summit microelectronics, inc. ?summit microelectronics, inc., 2000 ? 300 orchard city dr., suite 131 campbell, ca 95008 phone 408-378-6461 fax 408-378-6586 www.summitmicro.com soft starts main power supply on card insertion or system power up senses card insertion via short pins or ejector switches master enable to allow system control of power up or down can be used as a temperature sense input programmable independent controls of 3 dc/dc converters not enabled until host supply fully soft started programmable time delay between each enable signal available input to hold off dependant enables until conditions are satisfied highly programmable circuit breaker programmable quick-trip tm values programmable current limiting distributed power hot swap controller features simplified application drawing vdd vss cbsense pd1# pd2# uv ov pg3# 2.5vref pg2# pg1# 5.0vref 2051 sad 1.2 0v ?48v vgate pin detect pin detect dc/dc dc/dc dc/dc SMH4803A fault# enpga enpgb disable / enable drain sense r3 r1 r2 programmable circuit breaker mode: latched (volatile or nonvolatile) programmable duty cycle times programmable over-current filter programmable host voltage fault monitoring programmable under- voltage hysteresis programmable uv/ov voltage filter programmable fault mode: latched or duty cycle nonvolatile programming to customize features available pre-programmed from summit 2.5v and 5.0v reference outputs eliminates the need or other primary volt- ages easy expansion of external monitor func- tions supply range 20vdc to >500vdc
2 SMH4803A 2051 4.4 3/15/01 preliminary summit microelectronics, inc. functional block diagram programm- able delay programm- able delay programm- able delay + ? + ? + ? programmable quick trip ref. voltage 50mv fault latch and duty cycle timer filter + ? + ? 5v 2.5v 12v vgate sense + ? vdd vss mode reset# cbsense en/ts pd1# pd2# uv ov pg3# enpga enpgb 2.5vref pg2# pg1# drain sense vgate fault# 5.0vref 12vref 50k ? 200k ? 50k ? 2051 bd 1.3 3 4 5 15 16 20 12 11 1 10 8 7 9 6 2 18 13 19 17 14 50k ? 50k ? 50k ? 50k ? 3 2051 4.4 3/15/01 SMH4803A preliminary summit microelectronics, inc. pin configuration pin descriptions drain sense (1) the drain sense input monitors the voltage at the drain of the external power mosfet switch with respect to v ss . an internal 10a source pulls the drain sense signal towards the 5v reference level. drain sense must be held below 2.5v to enable the pg outputs. vgate (2) the vgate output activates an external power mosfet switch. this signal supplies a constant current output (100a typical), which allows easy adjustment of the mosfet turn on slew rate. en/ts (3) the enable/temperature sense input is the master en- able input. if en/ts is less than 2.5v, vgate will be disabled. this pin has an internal 200k ? pull-up to 5v. pd1# and pd2# (4 & 5) these are logic level active low inputs that can optionally be employed to enable vgate and the pg outputs when they are at v ss . these pins each have an internal 50k ? pull-up to 5v. fault# (6) this is an open-drain, active-low output that indicates the fault status of the device. reset# (7) reset# is used to clear latched fault conditions. when this pin is held low the vgate and pg outputs are disabled. refer to the circuit breaker operation and the associated timing diagrams for detailed characteristics. this pin has an internal 50k ? pull-up to 5v. mode (8) the state of the mode signal determines how fault conditions are cleared. the device is in the latched mode when the signal is held at v ss , and the cycle mode when held at 5v or left floating. this pin has an internal 50k ? pull-up to 5v. cbsense (9) the circuit breaker sense input is used to detect over- current conditions across an external, low value sense resistor (r s ) tied in series with the power mosfet. a voltage drop of greater than 50mv across the resistor for longer than t cbd will trip the circuit breaker. a program- mable quick-trip ? sense point is also available. 20-pin soic 2051 pcon 1.0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 drain sense vgate en/ts pd1# pd2# fault# reset# mode cbsense v ss v dd pg2# pg1# pg3# enpga enpgb 2.5vref 5.0vref ov uv product description the SMH4803A is an integrated solution for high reliability systems to monitor and react to events that could have a detrimental effect on a system. it can contain or limit faults to a single circuit board before that fault propagates to the system. its programmability lets a single board satisfy multiple circuit demands while customized to meet special requirements. the SMH4803A monitors and controls the primary voltage in a distributed power system while providing for both hot- swapping and secondary voltage sequencing in multi- supply systems. the primary power source can be shut down if events are sensed that could result in damage to either the circuit board or the system supply. an external fet switch is used to soft start the primary voltage once normal operating conditions are met. the external fet also uses an external shunt to monitor current for the circuit breaker function. the SMH4803A sequences secondary voltage by timed or externally controlled outputs that enable dc/dc con- verters. its reference voltages provide isolation between primary and secondary voltages, but allow expansion of its features. 4 SMH4803A 2051 4.4 3/15/01 preliminary summit microelectronics, inc. * comment stresses listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. temperature under bias ...................... ? 55 c to 125 c storage temperature ........................... ? 65 c to 150 c lead solder temperature (10s) ........................... 300 c terminal voltage with respect to v ss : vgate ......................................... v dd + 0.5v uv, ov, cbsense, drain sense, fault#, pg1#, pg2#, and pg3# ...................... ? 0.5v to v dd + 0.5v absolute maximum ratings* uv (11) the uv pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. vgate will be disabled if uv is less than 2.5v. program- mable internal hysteresis is available on the uv input, adjustable in increments of 62.5mv. also available is a filter delay on the uv input. ov (12) the ov pin is used as an over-voltage supply monitor, typically in conjunction with an external resistor ladder. vgate will be disabled if ov is greater than 2.5v. a filter delay is available on the ov input. 5.0vref & 2.5vref (13 & 14) these are precision 5v and 2.5v output reference volt- ages that may be use to expand the logic input functions on the SMH4803A. the reference outputs are with re- spect to v ss . enpga (16) this is an active high input that controls the pg2# and pg3# outputs. when enpga is pulled low the pg2# and pg3# outputs are immediately placed in a high impedance state. when enpga is driven high or left floating then pg2# will be driven low at a time period of t pgd after pg1# has been active. this pin has an internal 50k ? pull-up to 5v. enpgb (15) this is an active high input that controls the pg3# output. when enpgb is pulled low the pg3# output is immedi- ately placed in a high impedance state. when enpgb is driven high or left floating then pg3# will be driven low at a time period of t pgd after pg2# has been active. this pin has an internal 50k ? pull-up to 5v. pg1#, pg2#, & pg3# (18, 19, & 17) the pgn# pins are open-drain, active-low outputs with no internal pull-up resistor. they can be used to switch a load or enable a dc/dc converter. pg1# is enabled immedi- ately after vgate reaches v dd ? v gt and the drain sense voltage is less than 2.5v. each successive pg output is enabled t pgd after its predecessor, provided also that the appropriate enpg input(s) are high. voltage on these pins cannot exceed 12v, as referenced to v ss. v dd (20) v dd is the positive supply connection. an internal shunt regulator limits the voltage on this pin to approximately 12v with respect to vss. a resistor must be placed in series with the v dd pin to limit the regulator current (r d in the application illustrations). v ss (10) v ss is connected to the negative side of the supply. pd1#, pd2#, mode, reset#, enpga, enpgb, en/ts ......................... 10v recommended operating conditions temperature ? 40 c to 85 c. 5 2051 4.4 3/15/01 SMH4803A preliminary summit microelectronics, inc. dc operating characteristics ( over recommended operating conditions; voltages are relative to v ss , except v gt ) 2051 elect table 2.2 (1) ta = 25 c. l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u v d d e g a t l o v y l p p u si d d a m 3 =1 12 13 1v f e r v 0 . 5t u p t u o e c n e r e f e r v 5i d d a m 3 =5 7 . 40 0 . 55 2 . 5v i 5 d a o l t n e r r u c t u p t u o e c n e r e f e r v 5i d d a m 3 =1 ? 1a m f e r v 5 . 2t u p t u o e c n e r e f e r v 5 . 2 i d d a m 3 =) 1 (5 7 4 . 20 0 5 . 25 2 5 . 2v i d d a m 3 =5 2 4 . 20 0 5 . 25 7 5 . 2v i 5 . 2 d a o l t n e r r u c t u p t u o e c n e r e f e r v 5 . 2i d d a m 3 =2 . 0 ? 1a m i d d t n e r r u c y l p p u s r e w o pd e l b a n e t u p t u o2 0 1a m v v u d l o h s e r h t e g a t l o v - r e d n u i d d a m 3 =) 1 (5 7 4 . 20 0 5 . 25 2 5 . 2v i d d a m 3 =5 2 4 . 20 0 5 . 25 7 5 . 2v v t s y h v u s i s e r e t s y h e g a t l o v - r e d n ui d d a m 3 =0 1v m v v o d l o h s e r h t e g a t l o v - r e v o i d d a m 3 =) 1 (5 7 4 . 20 0 5 . 25 2 5 . 2v i d d a m 3 =5 2 4 . 20 0 5 . 25 7 5 . 2v v t s y h v o s i s e r e t s y h e g a t l o v - r e v oi d d a m 3 =0 1v m v e t a g v e g a t l o v t u p t u o e t a g v v d d v i e t a g v t u p t u o t n e r r u c e t a g v0 0 1a v e s n e s d l o h s e r h t e s n e s n i a r d i d d a m 3 =) 1 (5 7 4 . 20 0 5 . 25 2 5 . 2v i d d a m 3 =5 2 4 . 20 0 5 . 25 7 5 . 2v i e s n e s t u p t u o t n e r r u c e s n e s n i a r dv e s n e s v = s s ) 1 (9 0 11 1a v b c d l o h s e r h t r e k a e r b t i u c r i ci d d a m 3 =0 40 50 6v m v b c q t i u c r i c p i r t k c i u q e l b a m m a r g o r p d l o h s e r h t r e k a e r b 0 0 2v m 0 0 1v m 0 6v m f f o ? v s t n e d l o h s e r h t s t / n e i d d a m 3 =) 1 (5 7 4 . 20 0 5 . 25 2 5 . 2v i d d a m 3 =5 2 4 . 20 0 5 . 25 7 5 . 2v v t s y h s t n e s i s e r e t s y h s t / n ei d d a m 3 =0 1v m v h i , b / a g p n e : e g a t l o v h g i h t u p n i # t e s e r , e d o m 2f e r v 0 . 5v v l i , b / a g p n e : e g a t l o v w o l t u p n i # t e s e r , e d o m 1 . 0 ? 8 . 0v v l o # t l u a f : e g a t l o v w o l t u p t u oi l o a m 2 =0 4 . 0v # 3 / # 2 / # 1 g p : e g a t l o v w o l t u p t u oi k n i s a m 2 =0 4 . 0v v t g d l o h s e r h t e t a g7 . 08 . 10 . 3v 6 SMH4803A 2051 4.4 3/15/01 preliminary summit microelectronics, inc. general operation the SMH4803A is an integrated power controller for hot swappable add-in cards. the device operates from a wide supply range and generates the signals necessary to drive isolated output dc/dc converters. as a typical add-in board is inserted into the powered backplane physical connections must first be made with the chassis to dis- charge any electrostatic voltage potentials. the board then contacts the long pins on the backplane that provide power and ground. as soon as power is applied the device starts up, but does not immediately apply power to the output load. under-voltage and over-voltage circuits inside the controller check to see that the input voltage is within a user-specified range, and pin detection signals determine whether the card is seated properly. these requirements must be met for a pin detect delay period of t pdd , after which time the hot-swap controller enables vgate to turn on the external power mosfet switch. the vgate output is current limited to i vgate , allowing the slew rate to be easily modified using external passive components. during the controlled turn-on period the v ds of the mosfet is monitored by the drain sense input. when drain sense drops below 2.5v, and vgate gets above v dd ? v gt , the power good outputs can begin turning on the dc/dc controllers. power good enable inputs may be used to activate or deactivate specific output loads. steady state operation is maintained as long as all condi- tions are normal. any of the following events may cause the device to disable the dc/dc controllers by shutting down the power mosfet: an under-voltage or over- voltage condition on the host power supply; an over- current event detected on the cbsense input; a failure of the power mosfet sensed via the drain sense pin; the pin detect signals becoming invalid; or the master enable (en/ts) falling below 2.5v. the SMH4803A may be configured so that after any of these events occur the vgate output shuts off and either latches into an off state or recycles power after a cooling down period, t cyc . powering v dd the SMH4803A contains a shunt regulator on the v dd pin that prevents the voltage from exceeding 12v. it is necessary to use a dropper resistor (r d ) between the host power supply and the v dd pin in order to limit current into the device and prevent possible damage. the dropper resistor allows the device to operate across a wide range of system supply voltages, and also helps protect the device against common-mode power surges. refer to the applications section for help on calculating the r d resis- tance value. functional description system enables there are several enabling inputs, which allow a host system to control the SMH4803A. the pin detect pins (pd1# & pd2#) are two active low enables that are generally used to indicate that the add-in circuit card is properly seated. this is typically done by clamping the inputs to v ss through the implementation of an injector switch, or alternatively through the use of a staggered pins at the card-cage interface. two shorter pins arrayed at opposite ends of the connector force the card to be fully seated (not canted) before both pin detects are enabled. care must be taken not to exceed the maximum voltage rating of these pins during the insertion process. refer to details in the applications section for proper circuit imple- mentation. the en/ts input provides an active high comparator input that may be used as a master enable or temperature sense input. these inputs must be held low for a period of t pdd before a power-up sequence may be initiated. under-/over-voltage sensing the under-voltage (uv) and over-voltage (ov) inputs provide a set of comparators that act in conjunction with an external resistive divider ladder to sense when the host supply voltage exceeds the user defined limits. if the input to the uv pin rises above 2.5v, or the input to the ov pin falls below 2.5v for a period of t pdd , the power-up se- quence may be initiated. the t pdd filter helps prevent spurious start-up sequences while the card is being in- serted. if uv falls below 2.5v or ov rises above 2.5v, the pg and vgate outputs will be shut down immediately. under-/over-voltage filtering the SMH4803A may also be configured so that an out of tolerance condition on uv/ov will not shut off the output immediately. instead, a filter delay may be inserted so that only sustained under-voltage or over-voltage conditions will shut off the output. when the uv/ov filter option is enabled an out of tolerance condition on uv/ov for longer than the filter delay time, t uofltr , activates the fault# output, and the vgate and pg outputs will be latched in the off state. to initiate another power-up sequence the fault# output must first be reset. refer to the appropri- ate section on resetting the fault# output. the under- /over-voltage filtering feature is disabled in the default configuration of the device. under-voltage hysteresis the under-voltage comparator input may be configured with a programmable level of hysteresis. the compare 7 2051 4.4 3/15/01 SMH4803A preliminary summit microelectronics, inc. circuit breaker operation the SMH4803A provides a number of circuit breaker functions to protect against over current conditions. a sustained over-current event could damage the host sup- ply and/or the load circuitry. the board ? s load current passes through a series resistor (r s ) connected between the mosfet source (which is tied to cbsense) and v ss . the breaker trips whenever the voltage drop across r s is greater than 50mv for more than t cbd (a factory program- mable filter delay ranging from 10s to 500s). quick-trip tm circuit breaker additionally, the SMH4803A provides a quick-trip feature that will cause the circuit breaker to trip immediately if the voltage drop across r s exceeds v qcb . the quick-trip level may be factory set to 60mv, 100mv (default), 200mv, or the feature may be disabled. current regulation the current regulation mode is an optional feature that provides a means to regulate current through the mos- fet for a programmable period of time. if enabled the device will start the internal timer when the voltage at cbsense exceeds 50mv. also, it attempts to limit the voltage at cbsense to 60mv by regulating the vgate output. the circuit breaker will trip if the over-current condition remains after the time-out. however, if cb- sense drops below 50mv before the timer ends, the timer is reset and vgate resumes normal operation. if the quick-trip level is exceeded then the device will bypass the current regulation timer and shut down imme- diately. the current regulation feature is disabled in the default configuration. non-volatile fault latch the SMH4803A also provides an optional nonvolatile fault latch (nvfl) circuit breaker feature. the nonvolatile fault latch essentially provides a programmable fuse on the circuit breaker. when enabled the nonvolatile fault latch will be set whenever the circuit breaker trips. once set, it cannot be reset by cycling power or through the use of the reset# pin. n ote : t he device remains permanently disabled until it is reprogrammed at the factory . as long as the nvfl is set the fault# output will be driven active. the non-volatile fault latch feature is disabled in the default configuration. level may be set in steps (up to 15) of 62.5mv below 2.5v. the default under-voltage hysteresis level is set to 62.5mv. soft start slew rate control once all of the preconditions for powering up the dc/dc controllers have been met, the SMH4803A provides a means to soft start the external power fet. it is important to limit in-rush current to prevent damage to the add-in card or disruptions to the host power supply. for example, charging the filter capacitance (normally required at the input of the dc/dc controllers) too quickly may generate very high current. the vgate output of the SMH4803A is current limited to i vgate , allowing the slew rate to be easily modified using external passive components. the slew rate may be found by dividing i vgate by the gate-to- drain capacitance placed on the external fet. a complete design example is given in the applications section. load control ? sequencing the secondary sup- plies once power has been ramped to the dc/dc controllers, two conditions must be met before the pgn# outputs can be enabled: the drain sense voltage must be below 2.5v, and the vgate voltage must be greater than v dd ? v gt . the drain sense input helps ensure that the power mos- fet is not absorbing too much steady state power from operating at a high v ds . this sensor remains active at all times (except during the current regulation period). the vgate sensor makes sure that the power mosfet is operating well into its saturation region before allowing the loads to be switched on. once vgate reaches v dd ? v gt this sensor is latched. once the external mosfet is properly switched on the pgn# outputs may be enabled (if enpga and enpgb are both high). output pg1# is activated first, followed by pg2# after a delay of t pgd , and pg3# after another t pgd delay. the delays built into the SMH4803A allow timed sequencing of power to the loads. the delay times are factory programmed from 50s to 160ms. pg2# and pg3# can be disabled by bringing enpga low. likewise pg#3 is disabled when enpgb is low. this cascaded control is useful for enabling supplies that have dependencies based on the other voltages in the system. the pgn# outputs have a 12v withstand capability, so high voltages must not be connected to these pins. bipolar transistors or opto-isolators can be used to boost the withstand voltage to that of the host supply. see figures 10 and 11 for connections. 8 SMH4803A 2051 4.4 3/15/01 preliminary summit microelectronics, inc. timing relationships figure 1 illustrates some of the power on sequences, including the uv and ov differentials to their reference, and power good cascading. figure 1. complete power on timing sequence figures 2, 3, and 4 indicate the affect on the vgate signal caused by different circuit breaker inputs. in figure 2 reset# and mode are high; in figure 3 mode is low. figure 4 shows the quick trip mode. v dd 2051 fig01 1.1 uv ov pd1#/ pd2# vgate drain sense 2.5v ref 2.5v ref 11 v dd 13 t pdd pg1# pg2# pg3# enpgb t pgd 11 2051 4.4 3/15/01 SMH4803A preliminary summit microelectronics, inc. operating at high voltages the breakdown voltage of the external active and passive components limits the maximum operating voltage of the SMH4803A hot-swap controller. components that must be able to withstand the full supply voltage are: the input and output decoupling capacitors, the protection diode in series with the drain sense pin, the power mosfet switch and the capacitor connected between its drain and gate, the high-voltage transistors connected to the power good outputs, and the dropper resistor connected to the controller ? s v dd pin. over-voltage and under-voltage resistors in the following examples, the three resistors, r1, r2, and r3, connected to the ov and uv inputs, must be capable of withstanding the maximum supply voltage of several hundred volts. the trip voltage of the uv and ov inputs is 2.5v relative to v ss . as the input impedance of uv and ov is very high, large value resistors can be used in the resistive divider. the divider resistors should be high stability, 1% metal-film resistors to keep the under-voltage and over-voltage trip points accurate. telecom design example a hot-swap telecom application may use a 48v power supply with a ? 25% to +50% tolerance ( i.e. , the 48v supply can vary from 36v to 72v). the formulae for calculating r1, r2, and r3 follow. first a peak current, id max , must be specified for the resistive network. the value of the current is arbitrary, but it can't be too high (self-heating in r3 will become a problem), or too low (the value of r3 becomes very large, and leakage currents can reduce the accuracy of the ov and uv trip points). the value of id max should be 200a for the best accuracy at the ov and uv trip points. a value of 250a for id max will be used to illustrate the following calculations. with v ov (2.5v) being the over-voltage trip point, r1 is calculated by the formula: ov max v r1 id = . substituting: 2.5v r1 10k 250 a ==? . next the minimum current that flows through the resistive divider, id min , is calculated from the ratio of minimum and maximum supply voltage levels: max min min max id vs id vs = . substituting: min 250 a 36v id 125 a 72v == . now the value of r3 is calculated from id min : min uv min vs v r3 id ? = . v uv is the under-voltage trip point, also 2.5v. substituting: 36v 2.5v r3 268k 125 a ? ==? . the closest standard 1% resistor value is 267k ? then r2 is calculated: () uv min v r1 r2 id += , or uv min v r2 r1 id =? . substituting: 2.5v r2 10k 20k 10k 10k 125 a =??=???=? . an excel spread sheet is available on summit's website ( www.summitmicro.com ) to simplify the resistor value calculations and tolerance analysis for r1, r2, and r3. dropper resistor selection the SMH4803A is powered from the high-voltage supply via a dropper resistor, r d . the dropper resistor must provide the SMH4803A (and its loads) with sufficient operating current under minimum supply voltage condi- applications 12 SMH4803A 2051 4.4 3/15/01 preliminary summit microelectronics, inc. tions, but must not allow the maximum supply current to be exceeded under maximum supply voltage conditions. the dropper resistor value is calculated from: max min dd d dd load vs v r ii ? = + , where vs min is the lowest operating supply voltage, v ddmax is the upper limit of the SMH4803A supply voltage, i dd is minimum current required for the SMH4803A to operate, and i load is any additional load current from the 2.5v and 5v outputs and between v dd and v ss . the min/max current limits are easily met using the drop- per resistor, except in circumstances where the input voltage may swing over a very wide range ( e.g. , input varies between 20v and 100v). in these circumstances it may be necessary to add an 11v zener diode between v dd and v ss to handle the wide current range. the zener voltage should be below the nominal regulation voltage of the SMH4803A so that it becomes the primary regulator. mosfet v ds (on) threshold the drain sense input on the SMH4803A monitors the voltage at the drain of the external power mosfet switch with respect to v ss . when the mosfet ? s v ds is below the user-defined threshold the mosfet switch is considered to be on. the v ds (on) threshold is adjusted using the resistor, r t , in series with the drain sense protection diode. this protection, or blocking, diode prevents high voltage breakdown of the drain sense input when the mosfet switch is off. a low leakage mmbd1401 diode offers protection up to 100v. for high voltage applications (up to 500v) the central semiconductor cmr1f-10m diode should be used. the v ds (on) threshold is calcu- lated from: () ( ) ds sense sense t diode threshold von v i r v =?? , where v diode is the forward voltage drop of the protection diode. the v ds (on) threshold varies over temperature due to the temperature dependence of v diode and i sense . the calculation below gives the v ds (on) threshold under the worst case condition of 85 c ambient. using a 68k ? resistor for r t gives: () ( ) ds threshold von 2.5v15a68k 0.5v1v =? ??= . the voltage drop across the mosfet switch and sense resistor, v dss , is calculated from: () dss d s on virr =+ , where i d is the mosfet drain current, r s is the circuit breaker sense resistor, and r on is the mosfet on resistance. 13 2051 4.4 3/15/01 SMH4803A preliminary summit microelectronics, inc. figure 7. changing polarity of power good output pg1# note: figures 7 through 11 ? the *10 ? resistor must be located as close as possible to the mosfet 2.5v ref en/ts 100k ? mmbta06lt1 r t 68k ? 1k ? *10 ? 10nf 100v mmbd1401 100nf 100k ? mmbta06lt1 mmbta06lt1 100nf 50v 100nf 50v 10nf 100v uv ov pd1# pd2# fault# reset# v dd enpg a enpg b pg3# pg2# 5v ref SMH4803A pg1# v ss cbsense v gate drain sense 0v ? 48v 10k ? 10k ? r1 r d 6.8k ? 100f 100v r3 mode r2 r s 20m ? 47k ? 1n4148 0v ? 48v 2051 fig07 14 SMH4803A 2051 4.4 3/15/01 preliminary summit microelectronics, inc. figure 8. overtemperature shutdown 100k ? mmbta06lt1 r t 68k ? 1k ? *10 ? 10nf 100v mmbd1401 100nf 100k ? mmbta06lt1 100nf 50v 100nf 50v 10nf 100v uv ov pd1# pd2# fault# reset# v dd enpg a enpg b pg3# pg2# 5v ref SMH4803A pg1# v ss cbsense v gate drain sense 0v ? 48v 10k ? 10k ? r1 r d 6.8k ? 100f 100v r3 mode 1m ? r2 r s 20m ? 0v ? 48v 100k ? mmbta06lt1 2.5v ref en/ts + ? lmv331 1k ? 50k ? ntc 50k ? @t max 100nf 50v 2051 fig08 15 2051 4.4 3/15/01 SMH4803A preliminary summit microelectronics, inc. figure 9. expanding input monitoring capability note: figures 7 through 11 ? the *10 ? resistor must be located as close as possible to the mosfet 100k ? mmbta06lt1 r t 68k ? 1k ? *10 ? 10nf 100v mmbd1401 100nf 100k ? mmbta06lt1 100nf 50v 100nf 50v 10nf 100v uv ov pd1# pd2# fault# reset# v dd enpg a enpg b pg3# pg2# 5v ref SMH4803A pg1# v ss cbsense v gate drain sense 0v ? 48v 10k ? 10k ? r1 r d 6.8k ? 100f 100v r3 mode 1m ? r2 r s 20m ? 0v ? 48v 100k ? mmbta06lt1 2.5v ref en/ts 1k ? 100nf 50v + ? lmv 339 + ? + ? + ? en1 en4 en2 en3 10k ? 2051 fig09 16 SMH4803A 2051 4.4 3/15/01 preliminary summit microelectronics, inc. figure 10. typical application sequencing three dc/dc converters 100k ? mmbta06lt1 68k ? 1k ? *10 ? 10nf 100v mmbd1401 100nf 100k ? mmbta06lt1 100k ? mmbta06lt1 0v ? 48v +vin ? vin on/off +vout ? vout +vin ? vin on/off +vout ? vout +vin ? vin on/off +vout ? vout v3 v1 v2 uv ov pd1# pd2# v dd enpg a enpg b pg3# pg2# 5v ref SMH4803A pg1# v ss cbsense v gate drain sense 10k ? 10k ? r3 r2 r s r1 en/ts r d 6.8k ? 0v 100nf 50v isolated dc outputs 2051 fig10 dc / dc converters 10nf 100v 100f 100v 100nf 50v 17 2051 4.4 3/15/01 SMH4803A preliminary summit microelectronics, inc. figure 11. sequencing converters with common i/o ground and voltage feedback note: figures 7 through 11 ? the *10 ? resistor must be located as close as possible to the mosfet mmbta56lt1 68k ? 1k ? *10 ? 10nf 100v mmbd1401 100nf mmbta56lt1 0v ? 48v +vin ? vin on/off +vout ? vout +vin ? vin on/off +vout ? vout +vin ? vin on/off +vout ? vout v3 v1 v2 uv ov pd1# pd2# v dd enpg a enpg b pg3# pg2# 5v ref SMH4803A pg1# v ss cbsense v gate drain sense 10k ? 10k ? r3 r2 r s r1 en/ts r d 6.8k ? 0v 100nf 50v 2051 fig11 4.7k ? 4.7k ? 33k ? 33k ? reset reset reset1# reset2# 1n4148 1n4148 dc / dc converters 100nf 50v 100f 100v 100k ? 100k ? 100k ? 10nf 100v 18 SMH4803A 2051 4.4 3/15/01 preliminary summit microelectronics, inc. package 20 pin soic package 0.291 - 0.299 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.012 (0.10 - 0.30) 0.496 - 0.512 (12.60 - 13.00) 0.394 - 0.419 (10.00 - 10.65) 0.093 - 0.104 (2.35 - 2.65) 0.016 - 0.050 (0.40 - 1.27) (1.27) 0.009 - 0.013 (0.23 - 0.32) 0.010 - 0.029 (0.25 - 0.75) (7.40 - 7.60) 20pin soic 0 to 8 typ 45 o 0.016 - 0.050 0.05 0 to 8 typ ref. jedec ms-013 19 2051 4.4 3/15/01 SMH4803A preliminary summit microelectronics, inc. notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. this document supersedes all previous versions. ? copyright 2000 summit microelectronics, inc. ordering information SMH4803A s base part number package s = soic 2051 tree 2.0 |
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